`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:43:15 12/03/2020 
// Design Name: 
// Module Name:    ATReg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ATReg(
    input clk,
    input reset,
    input [4:0] newAddressIn,
    input [2:0] TnewIn,
    output reg[4:0] newAddressOut,
    output reg[2:0] TnewOut
    );

	always @(posedge clk)
	begin
		if(reset)begin
			newAddressOut <= 0;
			TnewOut <= 0;
		end
		else begin
			newAddressOut <= newAddressIn;
			TnewOut <= (TnewIn == 0) ? TnewIn : (TnewIn - 1);
		end
	end

endmodule
